Jameco-electronics Rabbit 3000 Instrukcja Użytkownika Pobierz pdf (Strona 167)

158 Rabbit 3000 Microprocessor

The MSB x registers for Timer B (TBM1R/TBM2R) are laid out as shown in Table 11-9.

The LSB x registers for Timer B (TBL1R/TBL2R) are laid out as shown in Table 11-10.

Table 11-9. Timer B Count MSB x Registers

Timer B Count MSB x Register (TBM1R) (Address = 0xB2)

(TBM2R) (Address = 0xB4)

Bit(s) Value Description

7:6 Write

The two MSBs of the comparae value for the Timer B comparator are stored.

This compare value will be loaded into the actual comparator when the current

compare detects a match.

5:0 These bits are always read as zeroes.

Table 11-10. Timer B Count LSB x Registers

Timer B Count LSB x Register (TBL1R) (Address = 0xB3)

(TBL2R) (Address = 0xB5)

Bit(s) Value Description

7:0 Write

The eight LSBs of the comparae value for the Timer B comparator are stored.

This compare value will be loaded into the actual comparator when the current

compare detects a match.

Table 11-11. Timer B Count MSB Register

Timer B Count MSB Register (TBCMR) (Address = 0xBE)

Bit(s) Value Description

7:6 Read The current value of the two MSBs of the Timer B counter are reported.

5:0 These bits are always read as zeroes.

Table 11-12. Timer B Count LSB Register

Timer B Count LSB Register (TBCLR) (Address = 0xBF)

Bit(s) Value Description

7:0 Read The current value of the eight LSBs of the Timer B counter are reported.

1 2 ... 162 163 164 165 166 167 168 169 170 171 172 ... 348 349

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Jameco-electronics Rabbit 3000 Instrukcja Użytkownika Strona 167